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8 - channel dac with pll and differential outputs, 192 khz, 24 bits data sheet ad1933 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted b y implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2007 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features pll generated or direct master clock low emi design dac with 110 db dynamic range and snr ?96 db thd + n 3.3 v single supply tolerance for 5 v logic inputs supports 24 bits and 8 khz to 192 khz sample rates differential dac output log volume cont rol with autoramp function spi? controllable for flexibility software - controllable clickless mute software power - down right - justified, left - justified, i 2 s, and tdm modes master and slave modes up to 16 - channel input/output 64- lead lqfp qualified for automo tive applications applications automotive audio systems home theater systems set - top boxes digital audio effects processors general description the ad1933 is a high performance, single chip that provides eight digital - to - analog converters (dacs) with diff erential output using the analog devices, inc., patented multibit sigma - delta ( - ) architecture. an spi port is included, allowing a microcontroller to adjust volume and many other parameters. the ad1933 operates from 3.3 v digital and analog supplies. th e ad1933 is available in a 64 - lead (differential output) lqfp. other members of this family include a single - ended dac output version. the ad1933 is designed for low emi. this consideration is apparent in both the system and circuit design architectures. by using the on - board pll to derive the master clock from the lr clock or from an external crystal, the ad1933 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. the dacs are designed using the latest analog devices continuous time architectures to further minimize emi. by using 3.3 v supplies, power consumption is minimized, further reducing emissions. functional block dia gram ad1933 6.144mhz analog audio outputs digi t a l audio input/output contro l d at a input/output digi t a l fi l ter and volume contro l seria l d at a port precision vo lt age reference clocks sd at ain contro l port spi timing management and contro l (clock and pull) dac dac dac dac dac dac dac dac 06624-001 figure 1.
ad1933 data sheet rev. e | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 test conditions ............................................................................. 3 analog performance specifications ........................................... 3 crystal oscillator specifications ................................................. 4 digital input/output specifications ........................................... 4 power supply specifications ........................................................ 5 digi tal filters ................................................................................. 5 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 11 digital - to - analog converters (dacs) .................................... 11 clock signals ............................................................................... 11 reset and power - down ............................................................. 11 serial control port ..................................................................... 12 power supply and voltage reference ....................................... 13 serial data ports data format ............................................... 13 ti me - division multiplexed (tdm) modes ............................ 13 daisy - chain mode ..................................................................... 15 control registers ............................................................................ 19 definitions ................................................................................... 19 pll and clock control registers ............................................. 19 dac control registers .............................................................. 20 auxiliary tdm port control registers ................................... 22 additional modes ....................................................................... 23 application circuits ....................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 automotive products ................................................................. 25 revision history 2 /1 3 rev. d to rev. e change s to t clh comments, table 7 ............................................... 6 changes to serial control port section ....................................... 12 10/11 rev. c to rev. d changes to pin 14 in figure 2 and table 10 .................................. 8 changes to ordering guide .......................................................... 25 added automotive products section ........................................... 25 7/11 rev. b to rev. c deleted reference to i 2 c ............................................... throughout changes to table 10, dsdatax/auxdata1 pin descriptions ...................................................................................... 8 1/11 rev. a to rev. b changes to features .......................................................................... 1 change to table summary, table 2 and table summary, table 4 .................................................................... 4 changes to table sum mary, table 7 ............................................... 6 9/09 rev. 0 to rev. a change to title ................................................................................... 1 change to table 10 ............................................................................ 9 change to power supply and voltage reference section .......... 13 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 25 10/07 revision 0: initial version
data sheet ad1933 rev. e | page 3 of 28 specifications test condition s performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specif ications. supply voltages (avdd, dvdd) 3.3 v temperature range 1 as specified in table 1 and table 2 master clock 12.288 mhz (48 khz f s , 256 f s mode) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance (digital output) 20 pf load current (digital output) 1 ma or 1.5 k ? to ? dvdd supply input voltage high 2.0 v input voltage low 0.8 v 1 functionally guaranteed at ?40c to +125c case temperature. analog performance s pecifications specifications guaranteed at an ambient temperature of 25c. table 1 . parameter test conditions/comments min typ max unit digita l - to - analog converters dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 102 107 db with a - weighted filter (rms) 105 110 db with a - weighted filter (avg) 112 db total harmonic distortion + noise 0 dbfs differential version two channels running ?96 db eight c hannels running ?86 ?76 db full - scale output voltage 1.76 (4.96) v rms (v p -p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ?25 ?6 +25 mv gain drift ?30 +30 ppm/c interchannel isolation 100 db interchannel phase deviation 0 degrees volume control step 0.375 db volume control range 95 db de - emphasis gain error 0.6 db output resistance at each pin 100 ? reference internal reference voltage filtr pin 1.50 v external reference volt age filtr pin 1.32 1.50 1.68 v common - mode reference output cm pin 1.50 v regulator input supply voltage vsupply pin 4.5 5.0 5.5 v regulated supply voltage vsense pin 3.19 3.37 3.55 v
ad1933 data sheet rev. e | page 4 of 28 specifications measured at a case temperature of 125c. table 2 . parameter test conditions/comments min typ max unit digital - to - analog converters dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 101 107 db with a - weighted filter (rms) 104 110 db with a - weighted filter (average) 112 db total harmonic distortion + noise 0 dbfs differential version two channels running ?94 db eigh t channels running ?86 ?70 db full - scale output voltage 1.76 (4.96) v rms (v p - p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ?25 ?6 +25 mv gain drift ?30 +30 ppm/c reference internal reference voltage filtr pin 1.50 v external reference voltage filtr pin 1.32 1.50 1.68 v common - mode reference output cm pin 1.50 v regulator input supply voltage vsupply pin 4.5 5.0 5.5 v regulated supply voltage vsense pin 3.2 3.43 3.65 v crystal oscilla tor specifications table 3 . parameter min typ max unit transconductance 3.5 mmhos digital input/output specifications ?40c < t c < +125c, dvdd = 3.3 v 10%. table 4 . parameter test conditions/comments min typ max unit high level input voltage (v ih ) 2.0 v high level input voltage (v ih ) mclki/xi pin 2.2 v low level input voltage (v il ) 0. 8 v input leakage i ih @ v ih = 2.4 v 10 a i il @ v il = 0.8 v 10 a high level output voltage (v oh ) i oh = 1 ma dvdd ? 0.60 v low level output voltage (v ol ) i ol = 1 ma 0.4 v input capacitance 5 pf
data sheet ad1933 rev. e | page 5 of 28 power supply specifi cations table 5 . parameter test conditions/comments min typ max unit supplies voltage dvdd 3.0 3.3 3.6 v avdd 3.0 3.3 3.6 v vsupply 4.5 5.0 5.5 v digital current master clock = 256 f s normal operation f s = 48 khz 56 ma f s = 96 khz 65 ma f s = 192 khz 95 ma power - down f s = 48 khz to 192 khz 2.0 ma analog current normal operation 74 ma power - down 23 ma dissipation operation master clock = 256 f s , 48 khz all supplies 429 mw digital supply 185 mw analog supply 244 mw power - down, all supplies 83 mw power supply rejection ratio signal at analog supply pins 1 khz, 200 mv p -p 50 db 20 khz, 200 mv p -p 50 db digital filters table 6 . parameter mode fac tor min typ max unit dac interpolation filter pass band 48 khz mode, typical @ 48 khz 0.4535 f s 22 khz 96 khz mode, typical @ 96 khz 0.3646 f s 35 khz 192 khz mode, typical @ 192 khz 0.3646 f s 70 khz pass - band ripple 48 khz mode, typical @ 48 khz 0.01 db 96 khz mode, typical @ 96 khz 0.05 db 192 khz mode, typical @ 192 khz 0.1 db transition band 48 khz mode, typical @ 48 khz 0.5 f s 24 khz 96 khz mode, typical @ 96 khz 0.5 f s 48 khz 192 khz mode, typical @ 192 khz 0 .5 f s 96 khz stop band 48 khz mode, typical @ 48 khz 0.5465 f s 26 khz 96 khz mode, typical @ 96 khz 0.6354 f s 61 khz 192 khz mode, typical @ 192 khz 0.6354 f s 122 khz stop - band attenuation 48 khz mode, typical @ 48 khz 70 db 96 khz mode, typical @ 96 khz 70 db 192 khz mode, typical @ 192 khz 70 db group delay 48 khz mode, typical @ 48 khz 25/ f s 521 s 96 khz mode, typical @ 96 khz 11/ f s 115 s 192 khz mode, typical @ 192 khz 8/ f s 42 s
ad1933 data sheet rev. e | page 6 of 28 timing specification s ?40c < t c < +125c, dvdd = 3.3 v 10%. table 7 . parameter condition comments min max unit input master clock (mclk) and reset t mh mclk duty cycle dac clock source = pll clock @ 256 f s , 384 f s , 512 f s , and 768 f s 40 60 % t mh dac clock s ource = direct mclk @ 512 f s (bypass on - chip pll) 40 60 % f mclk mclk frequency pll mode, 256 f s reference 6.9 13.8 mhz f mclk direct 512 f s mode 27.6 mhz t pdr rst low 15 ns t pdrr rst recovery reset to act ive output 4096 t mclk pll lock time mclk and lr clock input 10 ms 256 f s vco clock, output duty cycle mclko/xo pin 40 60 % spi port see figure 9 t cch cclk high 35 ns t ccl cclk low 35 ns f cclk cclk freq uency f cclk = 1/t ccp , only t ccp shown in figure 9 10 mhz t cds cin setup to cclk rising 10 ns t cdh cin hold from cclk rising 10 ns t cls clatch setup to cclk rising 10 ns t clh clatch hol d from cclk rising 10 ns t clhigh clatch high not shown in figure 9 10 ns t coe cout enable from cclk falling 30 ns t cod cout delay from cclk falling 30 ns t coh cout hold from cclk falling, not shown in figure 9 30 ns t cots cout tristate from cclk falling 30 ns dac serial port see figure 16 t dbh dbclk high slave mode 10 ns t dbl dbclk low slave mode 10 ns t dls dlrclk setup to dbclk rising, slave mode 10 ns t dlh dlrclk hold from dbclk rising, slave mode 5 ns t dls dlrclk skew from dbclk falling, master mode ?8 +8 ns t dds dsdata setup to dbclk rising 10 ns t ddh dsdata hold from dbclk rising 5 ns auxtdm serial port see figure 17 t abh auxtdmbclk high slave mode 10 ns t abl auxtdmbclk low slave mode 10 ns t als auxtdmlrclk setup to auxtdmbclk rising, slave mode 10 ns t alh auxtdmlrclk hold from auxtdmbclk rising, slave mode 5 ns t als auxtdmlrclk skew from auxtdmbclk falling, master mode ?8 +8 ns t dds dsdata setup to auxtdmbclk, not shown in figure 17 10 ns t ddh dsdata hold from auxtdmbclk rising, not shown in figure 17 5 ns auxiliary interface t dxdd auxdata delay from auxbclk falling 18 ns t xbh auxbclk high 10 ns t xbl auxbclk low 10 ns t dls auxlrclk setup to auxbclk rising 10 ns t dlh auxlrclk hold from auxbclk rising 5 ns
data sheet ad1933 rev. e | page 7 of 28 absolute maximum rat ings table 8 . parameter rati ng analog (avdd) ?0.3 v to +3.6 v digital (dvdd) ?0.3 v to +3.6 v vsupply ?0.3 v to +6.0 v input current (except supply pins) 20 ma analog input voltage (signal pins) ?0.3 v to avdd + 0.3 v digital input voltage (signal pins) ?0.3 v to dvdd + 0.3 v operating temper ature range (case) ?40c to +125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja represents thermal resis tance, junction - to - ambient; jc represents thermal resistance, junction - to - case. all characteristics are for a 4 - layer board. table 9 . thermal resistance package type ja jc unit 64- lead lqfp 47 11.1 c/w esd caution
ad1933 data sheet rev. e | page 8 of 28 pi n configuration and function description s nc 64 nc 63 avdd 62 lf 61 nc 60 nc 59 nc 58 nc 57 nc 56 nc 55 nc 54 nc 53 cm 52 avdd 51 nc 50 nc 49 dvdd 17 dsdata3 18 dsdata2 19 dsdata1 20 dbclk 21 dlrclk 22 vsupply 23 vsense 24 vdrive 25 auxdata1 26 nc 27 auxtdmbclk 28 auxtdmlrclk 29 cin 30 cout 31 dvdd 32 agnd 1 mclki/xi 2 mclko/xo 3 agnd 4 avdd 5 ol3p 6 ol3n 7 or3p 8 or3n 9 ol4p 10 ol4n 11 or4p 12 or4n 13 rst 14 dsdata4 15 dgnd 16 agnd 48 filtr 47 agnd 46 avdd 45 agnd 44 or2n 43 or2p 42 ol2n 41 ol2p 40 or1n 39 or1p 38 ol1p 36 clatch 35 cclk 34 dgnd 33 ol1n 37 ad1933 top view (not to scale) differential output nc = no connect 06624-002 figure 2 . pin configuration table 10 . pin function descriptions pin no. input/output mnemonic description 1 i agnd analog ground. 2 i mclki/xi master clock inpu t/crystal oscillator input. 3 o mclko/xo master clock output/crystal oscillator output. 4 i agnd analog ground. 5 i avdd analog power supply. connect to analog 3.3 v supply. 6 o ol3p dac 3 left positive output. 7 o ol3n dac 3 left negative output. 8 o or3p dac 3 right positive output. 9 o or3n dac 3 right negative output. 10 o ol4p dac 4 left positive output. 11 o ol4n dac 4 left negative output. 12 o or4p dac 4 right positive output. 13 o or4n dac 4 right negative output. 14 i rs t reset (active low). 15 i/o dsdata4 dacserial data input 4. input to dac4 data in/tdm dac2 data out (dual - line mode)/aux dac2 data out (to external dac2). 16 i dgnd digital ground. 17 i dvdd digital power supply. connect to digital 3.3 v supply. 18 i/o dsdata3 dac serial data input 3. data input to dac3 in/tdm dac2 data in (dual - line mode)/aux not used. 19 i/o dsdata2 dac serial data input 2. data input to dac2 data in/tdm dac data out/aux not used. 20 i dsdata1 dac serial data input 1. data input to dac1 data in/tdm dac data in/aux tdm data in. 21 i/o dbclk bit clock for dacs. regular stereo, tdm, or daisy - chain tdm mode. 22 i/o dlrclk lr clock for dacs. regular stereo, tdm, or daisy - chain tdm mode.
data sheet ad1933 rev. e | page 9 of 28 pin no. input/output mnemonic description 23 i vsupply 5 v input to regulator, emitter of pass transistor. 24 i vsense 3.3 v output of regulator, collector of pass transistor. 25 o vdrive drive for base of pass transistor. 26 o auxdata1 aux dac1 data out (to external dac1). 27, 49, 50, 63, 64 nc no connect. 28 i/o auxtdmbclk auxiliary mode only dac tdm bit clock. 29 i/o auxtdmlrclk auxiliary mode only dac lr tdm clock. 30 i cin control data input (spi). 31 i/o cout control data output (spi). 32 i dvdd digital power supply. connect to digital 3.3 v supply. 33 i dgnd digital ground. 34 i cclk control clock input (spi). 35 i clatch latch input for control data (spi). 36 o ol1p dac 1 left positive output. 37 o ol1n dac 1 left negative output. 38 o or1p dac 1 right positive output. 39 o or1n dac 1 right negative output. 40 o ol2p dac 2 left positive output. 41 o ol2n dac 2 left negative output. 42 o or2p dac 2 right positive output. 43 o or2n dac 2 right negative output. 44 i agnd analog ground. 45 i avdd analog power supply. connect to analog 3.3 v supply. 46 i agnd analog ground. 47 o f i ltr voltage reference filter capacitor connection . bypass with 10 f||100 nf to agnd. 48 i agnd analog ground. 51 i avdd analog power supply. connect to analog 3.3 v supply. 52 o cm common - mode reference filter capacito r connection. bypass with 47 f||100 nf to agnd. 53 to 60 i nc must be tied to common mode, pin 52. alternately, ac - couple these pins to ground. 61 o lf pll loop filter, return to avdd. 62 i avdd analog power supply. connect to analog 3.3 v supply.
ad1933 data sheet rev. e | page 10 of 28 typical performance characteristics 0.06 0.04 0.02 ?0.06 ?0.04 ?0.02 0 0 24 16 8 magnitude (db) frequency (khz) 06624-003 figure 3 . dac pass- band filter response, 48 khz 0 ?150 ?100 ?50 0 48 12 24 36 magnitude (db) frequenc y (khz) 06624-004 figure 4 . dac stop- band filter response, 48 khz 0.10 ?0.10 ?0.05 0 0.05 0 96 72 48 24 magnitude (db) frequency (khz) 06624-005 figure 5 . dac pass- band filter respo nse, 96 khz 0 ?150 ?100 ?50 0 96 24 48 72 magnitude (db) frequency (khz) 06624-006 figure 6 . dac stop- band filter response, 96 khz 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 64 8 16 32 magnitude (db) frequency (khz) 06624-007 figure 7 . dac pass- band filter response, 192 khz ?10 ?8 ?6 ?4 ?2 0 48 96 64 80 magnitude (db) frequency (khz) 06624-008 figure 8 . dac stop- band filter response, 192 khz
data sheet ad1933 rev. e | page 11 of 28 theory of operation digital - to - analog converters (d ac s ) the ad1933 dac channels are arranged as differential, four stereo pairs giving eight analog outputs for minimum external components. the dacs include on - board digital reconstruction filters with 70 db stop - band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 khz or 96 khz modes) or 2 (192 khz mode). each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 db. digital i nputs are supplied through four serial data input pins (one for each stereo pair) and a common frame clock (dlrclk) and bit clock (dbclk). alternatively, one of the tdm modes can be used to access up to 16 channels on a si ngle tdm data line. each output pi n has a nominal common - mode dc level of 1.5 v and swings 1.27 v for a 0 dbfs digital input signal. a third - order, external, low - pass filter is recommended to remove high frequency noise present on the output pins. the use of op amps with low slew rates or low bandwidths can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. the voltage at cm, the common - mode reference pin, can be used to bias the external op amps that buffer the ou tput signals (see the power supply and voltage reference section). clock signals the on - chip, phase - locked loop (pll) can be selected to reference the input sample rate from either of the lrclk pins or 256, 384, 512, or 768 tim es the sample rate, referenced to the 48 khz mode from the mclki/xi pin. the default at power - up is 256 f s from mclki/xi pin. in 96 khz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is di vided by 2. in 192 khz mode, the actual multiplication rate is divided by 4. for example, if a device in the ad1933 family is programmed in 256 f s mode, the frequency of the master clock input is 256 48 khz = 12.288 mhz. if the ad1933 is then switched to 96 khz operation (by writing to the spi port), the frequency of the master clock should remain at 12.288 mhz, which becomes 128 f s . in 192 khz mode, this becomes 64 f s . the internal clock for the dacs varies by mode: 512 f s (48 khz mode), 256 f s (96 khz mode), or 128 f s (192 khz mode). by default, the on - board pll generates this internal master clock from an external clock. a direct 512 f s ( referenced to 48 khz mode) master clock can be used for dacs if selected in the pll and clock control 1 register. the pll can be powered down in the pll and clock control 0 register. to ensure reliable locking when changing pll modes, or if the reference clock is unstable at power - on, power down the pll and power it back up when the reference clock has sta bilized. the internal master clock can be disabled in the pll and clock control 0 register to reduce power dissipation when the ad1933 is idle. the clock should be stable before it is enabled. unless a standalone mode is selected (see the serial control port section), the clock is disabled by reset and must be enabled by writing to the spi port for normal operation. to maintain the highest performance possible, limit the clock jitter of the i nternal master clock signal to less th an a 300 ps rms time interval error (tie). even at these levels, extra noise or tones can appear in the dac outputs if the jitter spectrum contains large spectral peaks. if the internal pll is not used, it is highly recommended that an independent crystal oscillator generate the master clock. in addition, it is especially important that the clock signal not be passed through an fpga, cpld, or other large digital chip (such as a dsp) before being applied to the ad1933. in most cases, this induces clock jitt er due to the sharing of common power and ground connections with other unrelated digital output signals. when the pll is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. reset and power - down the fun ction of the rst pin sets all the control registers to their default settings. to avoid pops, reset does not power down the analog outputs. after rst is deasserted, and the pll acquires lock condition, an initialization routine runs inside the ad1933. this initialization lasts for approximately 256 master clock cycles. the power - down bits in the pll and clock control 0 and dac control 1 registers power down the respective sections. all other register settings are retained . to guarantee proper startup, the rst pin should be pulled low by an external resistor.
ad1933 data sheet rev. e | page 12 of 28 serial control port the ad1933 has an spi control port that permits programming and reading back of the internal control registers for the adcs, dacs, and clock system. a standalone mode is also available for operation without serial control; standalone is configured at reset by connecting cin, cclk, and clatch to ground. in standalone mode, all registers are set to default, except the internal mclk enable, which is set to 1. the adc abclk and alrclk clock ports are set to master/slave by the connecting the cout pin to either dvdd or ground. standalone mode only supports stereo mode with an i 2 s data format and 256 f s mclk rate. refer to table 11 for details. if cin, cclk, and clatch are not grounded, the ad1933 spi port is active. it is recommended to use a weak pull-up resistor on clatch in applications that have a microcontroller. this pull-up resistor ensures that the ad1933 recognizes the presence of a micro- controller. the spi control port of the ad1933 is a 4-wire serial control port. the format is similar to the motorola spi format except the input data-word is 24 bits wide. the serial bit clock and latch can be completely asynchronous to the sample rate of the dacs. figure 9 shows the format of the spi signal. the first byte is a global address with a read/write bit. for the ad1933, the address is 0x04, shifted left 1 bit due to the r/ w bit. the second byte is the ad1933 register address and the third byte is the data. d0 d0 d8 d8 d22 d23 d9 d9 c latch cclk cin cout t cch t ccl t cds t cdh t cls t ccp t clh t cots t cod t coe 06624-009 figure 9. format of spi signal
data sheet ad1933 rev. e | page 13 of 28 power supply and voltage reference the ad1933 is designed for 3.3 v supplies. separate power supply pins are provided for the analog and digital sections. these pins should be bypassed with 100 nf ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pcb as the dac. for critical applications, improved performance is obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. it is important that the analog supply be as clean as possible. the ad1933 includes a 3.3 v regulator driver that only requires an external pass transistor and bypass capacitors to make a 5 v to 3.3 v regulator. if the regulator driver is not used, connect vsupply, vdrive, and vsense to dgnd. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the 3.3 v dvdd supply and are compatible with ttl and 3.3 v cmos levels. the dac internal voltage reference (vref) is brought out on filtr and should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. any external current drawn should be limited to less than 50 a. the internal reference can be disabled in the pll and clock control 1 register and filtr can be driven from an external source. this can be used to scale the dac output to the clipping level of a power amplifier based on its power supply voltage, dac output gain is proportional to the filtr voltage. the cm pin is the internal common-mode reference. it should be bypassed as close as possible to the chip, with a parallel combination of 47 f and 100 nf. this voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. the output current should be limited to less than 0.5 ma source and 2 ma sink. serial data portsdata format the eight dac channels use a common serial bit clock (dbclk) and a common left-right framing clock (dlrclk) in the serial data port. the clock signals are all synchronous with the sample rate. the normal stereo serial modes are shown in figure 15. the dac serial data modes default to i 2 s. the ports can also be programmed for left-justified, right-justified, and tdm modes. the word width is 24 bits by default and can be programmed for 16 or 20 bits. the dac serial formats are programmable according to the dac control 0 register. the polarity of the dbclk and dlrclk is programmable according to the dac control 1 register. the auxiliary tdm port is also provided for applications requiring more than eight dac channels. in this mode, the auxtdmlrclk and auxtdmbclk pins are configured as tdm port clocks. in regular tdm mode, the dlrclk and dbclk pins are used as the tdm port clocks. the auxiliary tdm serial port format and its serial clock polarity are programmable according to the auxiliary tdm port control 0 register and the auxiliary tdm port control 1 register. both dac and auxiliary tdm serial ports are programmable to become the bus masters according to the dac control 1 register and auxiliary tdm control 1 register. by default, both auxiliary tdm and dac serial ports are in slave mode. time-division multiplexed (tdm) modes the ad1933 serial ports have several different tdm serial data modes. the most commonly used configuration is shown in figure 10. in figure 10, the eight on-chip dac data slots are packed into one tdm stream. in this mode, dbclk is 256 f s . the i/o pins of the serial ports are defined according to the serial mode selected. for a detailed description of the function of each pin in tdm and auxiliary modes, see table 11. the ad1933 allows systems with more than eight dac channels to be easily configured by the use of an auxiliary serial data port. the dac tdm-aux mode is shown in figure 11. in this mode, the aux channels are the last four slots of the 16-channel tdm data stream. these slots are extracted and output to the aux serial port. one major difference between the tdm mode and an auxiliary tdm mode is the assignment of the tdm port pins, as shown in table 11. in auxiliary tdm mode, dbclk and dlrclk are assigned as the auxiliary port clocks, and auxtdmbclk and auxtdmlrclk are assigned as the tdm port clocks. in regular tdm or 16-channel, daisy-chain tdm mode, the dlrclk and dbclk pins are set as the tdm port clocks. it should be noted that due to the high auxtdmbclk frequency, 16-channel auxiliary tdm mode is available only in the 48 khz/44.1 kh z/32 khz sample rate. slot 1 left 1 slot 2 right 1 slot 3 left 2 slot 4 right 2 msb msb?1 msb?2 data bclk lrclk slot 5 left 3 slot 6 right 3 slot 7 left 4 slot 8 right 4 lrcl k bclk data 256 bclks 32 bclk 06624-010 figure 10. dac tdm (8-channel i 2 s mode)
ad1933 data sheet rev. e | page 14 of 28 table 11. pin function changes in tdm-aux mode pin name stereo modes tdm modes aux modes auxdata1 not used (float) not used (float) aux data out 1 (to external dac 1) dsdata1 dac 1 data in dac tdm data in tdm data in dsdata2 dac 2 data in dac tdm data out not used (ground) dsdata3 dac 3 data in dac tdm data in 2 (dual-line mode) not used (ground) dsdata4 dac 4 data in dac tdm data out 2 (dual-line mode) aux data out 2 (to external dac 2) auxtdmlrclk not used (ground) not used (ground) tdm frame sync in/tdm frame sync out auxtdmbclk not used (ground) not used (ground) tdm bclk in/tdm bclk out dlrclk dac lrclk in/dac lrclk out dac tdm frame sync in/dac tdm frame sync out aux lrclk in/aux lrclk out dbclk dac bclk in/dac bclk out dac tdm bclk in/dac tdm bclk out aux bclk in/aux bclk out left right msb msb msb msb auxtdmlrclk auxtdmbclk dsdata1 (tdm_in) dlrclk (aux port) dbclk (aux port) auxdata1 (aux1_out) dsdata4 (aux2_out) msb empty empty empty empty dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 aux l1 aux r1 aux l2 aux r2 8-on-chip dac channels auxiliary dac channels will appear at aux dac ports unused slots 32 bits 0 6624-011 figure 11. 16-channe l dac tdm-aux mode
data sheet ad1933 rev. e | page 15 of 28 daisy-chain mode the ad1933 also allows a daisy-chain configuration to expand the system 16 dacs (see figure 12). in this mode, the dbclk frequency is 512 f s . the first eight slots of the dac tdm data stream belong to the first ad1933 in the chain and the last eight slots belong to the second ad1933. the second ad1933 is the device attached to the dsp tdm port. to accommodate 16 channels at a 96 khz sample rate, the ad1933 can be configured into a dual-line, dac tdm mode, as shown in figure 13. this mode allows a slower dbclk than normally required by the one-line tdm mode. again, the first four channels of each tdm input belong to the first ad1933 in the chain and the last four channels belong to the second ad1933. the dual-line, dac tdm mode can also be used to send data at a 192 khz sample rate into the ad1933, as shown in figure 14. the i/o pins of the serial ports are defined according to the serial mode selected. see table 12 for a detailed description of the function of each pin. see figure 18 for a typical ad1933 configuration with two external stereo dacs. figure 15 and figure 16 show the serial mode formats. for maximum flexibility, the polarity of lrclk and bclk are programmable. in these figures, all of the clocks are shown with their normal polarity. the default mode is i 2 s. dlrclk dbclk 8 dac channels of the first ic in the chain 8 unused slots 8 dac channels of the second ic in the chain msb dsdata1 (tdm_in) of the second ad1933 dsdata2 (tdm_out) of the second ad1933 this is the tdm to the first ad1933 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 32 bits dsp second ad1933 first ad1933 06624-012 figure 12. single-line dac tdm daisy-chain mode (applicable to 48 khz sample rate, 16-channel, two ad1933 daisy chain) dlrclk dbclk 8 dac channels of the second ic in the chain 8 dac channels of the first ic in the chain dsdata1 (in) dac l1 dac r1 dac l2 dac r2 dac l1 dac r1 dac l2 dac r2 dsdata3 (in) dac l3 dac r3 dac l4 dac r4 dac l3 dac r3 dac l4 dac r4 dsdata2 (out) dac l1 dac r1 dac l2 dac r2 dsdata4 (out) dac l3 dac r3 dac l4 dac r4 32 bits dsp second ad1933 first ad1933 msb 06624-013 figure 13. dual-line, dac tdm mode (applicable to 96 khz sample rate, 16-channel, two ad1933 daisy chain; dsdata3 and dsdata4 a re the daisy chain)
ad1933 data sheet rev. e | page 16 of 28 06624-014 dlrclk dbclk dsdata1 dac l1 dac r1 dac l2 dac r2 dsdata2 dac l3 dac r3 dac l4 dac r4 32 bits msb figure 14. dual-line, dac tdm mode (applicable to 192 khz sample rate, 8-channel mode) lrclk bclk sdat a lrclk bclk sdat a lrclk bclk sdat a lsb lsb lsb lsb lsb lsb left channel right channel right channel left channel left channel right channel msb msb msb msb msb msb right-justified mode?select number of bits per channel dsp mode?16 bits to 24 bits per channel i 2 s-justified mode?16 bits to 24 bits per channel left-justified mode?16 bits to 24 bits per channel lrclk bclk sdat a lsb lsb notes 1. dsp mode does not identify channel. 2. lrclk normally operates at f s except for dsp mode, which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. msb msb 1/ f s 06624-015 figure 15. stereo serial modes
data sheet ad1933 rev. e | page 17 of 28 dbclk dlrclk dsdata left-justified mode dsdata right-justified mode dsdata i 2 s-justified mode t dlh t dbh t dbl t dls t dds msb msb msb lsb msb?1 t ddh t dds t ddh t dds t ddh t ddh t dds 06624-016 figure 16. dac serial timing auxtdmbclk auxtdmlrclk dsdata1 left-justified mode dsdata1 right-justified mode dsdata1 i 2 s-justified mode t abh lsb msb msb msb msb?1 t abl t als t alh 06624-017 figure 17. auxtdm serial timing
ad1933 data sheet rev. e | page 18 of 28 table 12 . pin fu nction changes in tdm - aux mode (replication of table 11) pin name stereo modes tdm modes aux modes auxdata1 not used (float) not used (float) aux data out 1 (to external dac 1) dsdata1 dac 1 data in dac tdm data in tdm data i n dsdata2 dac 2 data in dac tdm data out not used (ground) dsdata3 dac 3 data in dac tdm data in 2 (dual - line mode) not used (ground) dsdata4 dac 4 data in dac tdm data out 2 (dual - line mode) aux data out 2 (to external dac 2) auxtdmlrclk not used ( ground) not used (ground) tdm frame sync in/tdm frame sync out auxtdmbclk not used (ground) not used (ground) tdm bclk in/tdm bclk out dlrclk dac lrclk in/dac lrclk out dac tdm frame sync in/dac tdm frame sync out aux lrclk in/aux lrclk out dbclk dac bc lk in/dac bclk out dac tdm bclk in/dac tdm bclk out aux bclk in/aux bclk out aux dac 1 aux dac 2 lrclk bclk data mclk lrclk bclk data mclk 30mhz 12.288mhz sharc is running in slave mode (interrupt-driven) sharc ad1933 tdm master aux master fsync-tdm (rfs) rxclk txclk txdata tfs (nc) auxdata1 dsdata4 dbclk dlrclk dsdata2 dsdata3 mclki/xi auxtdmlrclk auxtdmbclk dsdata1 06624-018 figure 18 . example of aux mode connection to sharc? (ad1933 as tdm master/aux master shown)
data sheet ad1933 rev. e | page 19 of 28 control registers definitions the global address for the ad1933 is 0x04, shifted left 1 bit due to the r/ w bit. all registers are reset to 0, except for the dac volume registers that are set to full volume. note that the first setting in each control register parameter is the default setting. table 13 . register format global address r/ w register address data bit 23:17 16 15:8 7:0 table 14 . register addresses and functions address function 0 pll and clock control 0 1 pll and clock control 1 2 dac control 0 3 dac control 1 4 dac control 2 5 dac individual channel mutes 6 dac l1 volume control 7 dac r1 volume control 8 dac l2 volume control 9 dac r2 volume control 10 dac l3 volume control 11 dac r3 volume control 12 dac l4 volume control 13 dac r4 volume control 14 reserved 15 auxiliary tdm port control 0 16 auxiliary tdm port control 1 pll and clock contro l registers table 15 . pll and clock control 0 bit value function description 0 0 n ormal operation pll power - down 1 power - down 2:1 00 input 256 (44.1 khz or 48 khz) mclki/xi pin functionality (pll active), master clock rate setting 01 input 384 (44.1 khz or 48 khz) 10 input 512 (44.1 khz or 48 khz) 11 input 768 (44.1 kh z or 48 khz) 4:3 00 xtal oscillator enabled mclko/xo pin, master clock rate setting 01 256 f s vco output 10 512 f s vco output 11 off 6:5 00 mclki/xi pll input 01 dlrclk 10 auxtdmlrclk 11 reserved 7 0 disable: dac idle internal m aster clock enable 1 enable: dac active
ad1933 data sheet rev. e | page 20 of 28 table 16 . pll and clock control 1 bit value function description 0 0 pll clock dac clock source select 1 mclk 1 0 pll clock clock source select 1 mclk 2 0 enabled on - chip voltag e reference 1 disabled 3 0 not locked pll lock indicator (read - only) 1 locked 7:4 0000 reserved dac control register s table 17 . dac control 0 bit value function description 0 0 normal power - down 1 power - down 2:1 00 32 khz/44.1 khz/48 khz sample rate 01 64 khz/88.2 khz/96 khz 10 128 khz/176.4 khz/192 khz 11 reserved 5:3 000 1 sdata delay (bclk periods) 001 0 010 8 011 12 100 16 101 reserved 110 reserved 111 reserved 7:6 00 stereo (norm al) serial format 01 tdm (daisy chain) 10 dac aux mode (dac - , tdm- coupled) 11 dual - line tdm table 18 . dac control 1 bit value function description 0 0 latch in midcycle (normal) bclk active edge (tdm in) 1 latch in at end of cycle (pipeline) 2:1 00 64 (2 channels) bclks per frame 01 128 (4 channels) 10 256 (8 channels) 11 512 (16 channels) 3 0 left low lrclk polarity 1 left high 4 0 slave lrclk master/slave 1 master 5 0 slave bclk master/slave 1 m aster 6 0 dbclk pin bclk source 1 internally generated 7 0 normal bclk polarity 1 inverted
data sheet ad1933 rev. e | page 21 of 28 table 19 . dac control 2 bit value function description 0 0 unmute master mute 1 mute 2:1 00 flat de - emphasis (32 khz/44.1 khz/ 48 khz mode only) 01 48 khz curve 10 44.1 khz curve 11 32 khz curve 4:3 00 24 word width 01 20 10 reserved 11 16 5 0 noninverted dac output polarity 1 inverted 7:6 00 reserved table 20 . dac individual chan nel mutes bit value function description 0 0 unmute dac 1 left mute 1 mute 1 0 unmute dac 1 right mute 1 mute 2 0 unmute dac 2 left mute 1 mute 3 0 unmute dac 2 right mute 1 mute 4 0 unmute dac 3 left mute 1 mute 5 0 unmute dac 3 right mute 1 mute 6 0 unmute dac 4 left mute 1 mute 7 0 unmute dac 4 right mute 1 mute table 21 . dac volume controls bit value function description 7:0 0 no attenuation dac volume control 1 to 254 ?3/8 db per step 255 full attenuation
ad1933 data sheet rev. e | page 22 of 28 auxiliary tdm port c ontrol registers table 22 . auxiliary tdm control 0 bit value function description 1:0 00 24 word width 01 20 10 reserved 11 16 4:2 000 1 sdata delay (bclk periods) 001 0 010 8 011 12 100 16 101 reserved 110 reserved 111 reserved 6:5 00 reserved serial format 01 reserved 10 dac aux mode 11 reserved 7 0 latch in midcycle (normal) bclk active edge (tdm in) 1 latch in at end of cycle (pipeline) tabl e 23 . auxiliary tdm control 1 bit value function description 0 0 50/50 (allows 32, 24, 20, or 16 bit clocks (bclks) per channel) lrclk format 1 pulse (32 bclks per channel) 1 0 drive out on falling edge (def) bclk polarity 1 drive out on rising edge 2 0 left low lrclk polarity 1 left high 3 0 slave lrclk master/slave 1 master 5:4 00 64 bclks per frame 01 128 10 256 11 512 6 0 slave bclk master/slave 1 master 7 0 auxtdmbclk pin bclk source 1 internall y generated
data sheet ad1933 rev. e | page 23 of 28 additional modes the ad1933 offers several additional modes for board level design enhancements. to reduce the emi in board level design, serial data can be transmitted without an explicit bclk. see figure 19 for an example of a dac tdm data transmission mode that does not require high speed dbclk. this configu- ration is applicable when the ad1933 master clock is generated by the pll with the dlrclk as the pll reference frequency. to relax the requirement for the setup time of the ad1933 in cases of high speed tdm data transmission, the ad1933 can latch in the data using the falling edge of dbclk. this effectively dedicates the entire bclk period to the setup time. this mode is useful in cases where the source has a large delay time in the serial data driver. figure 20 shows this pipeline mode of data trans- mission. both the blck-less and pipeline modes are available. dlrclk internal dbclk dsdatax dlrclk internal dbclk t dm-dsdatax 32 bits 06624-019 figure 19. serial dac data transmission in tdm format without dbclk (applicable only if pll locks to dlrclk) dlrclk dbclk dsdatax data must be valid at this bclk edge msb 06624-020 figure 20. i 2 s pipeline mode in dac serial data transmission (applicable in stereo and tdm useful for high frequency tdm transmission)
ad1933 data sheet rev. e | page 24 of 28 application circuits t ypical applications circuits are shown in figure 21 through figure 23. figure 21 shows the recommended loop filters when using either the lr clock or the master clock as th e pll reference. output filters for the dac outputs are shown in figure 22 and the regulator circuit is shown in figure 23. 39nf + 2.2nf lf lrclk avdd2 3.32k? 5.6nf 390pf lf mclk avdd2 562? 06624-021 figure 21 . recommended loop filters for lrclk or mclk pll reference 2 1 3 op275 ? + 2.2nf npo audio output 604? 68pf npo 150pf npo 560pf npo 270pf npo dac outn 3.01k? 11k? dac outp 1.50k? 5.62k? 11k? 5.62k? 06624-022 figure 22 . typical dac output filter circuit (differential) 10f + e c b vsupply 5v vsense 3.3v fzt953 vdrive 1k? 100nf 10f + 100nf 06624-023 figure 23 . recommended 3.3 v regulator circuit
data sheet ad1933 rev. e | page 25 of 28 outline dimensions compliant to jedec standards ms-026-bcd 051706-a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 11.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 0 . 1 5 0 . 0 5 7 3.5 0 figure 24. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model 1, 2, 3 temperature range package description package option ad1933ystz ?40c to +105c 64-lead lqfp st-64-2 ad1933ystz-rl ?40c to +105c 64-lead lqfp, 13 tape and reel st-64-2 ad1933wbstz ?40c to +105c 64-lead lqfp st-64-2 ad1933wbstz-rl ?40c to +105c 64-lead lqfp, 13 tape and reel st-64-2 EVAL-AD1939AZ evaluation board 1 z = rohs compliant part. 2 the EVAL-AD1939AZ should be used as the evaluation board for the ad1933. the ad1933 is a dac-only equiva lent to the ad1939. 3 w = qualified for auto motive applications. automotive products the ad1933w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
ad1933 data sheet rev. e | page 26 of 28 notes
data sheet ad1933 rev. e | page 27 of 28 notes
ad1933 data sheet rev. e | page 28 of 28 notes ? 2007 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06624 - 0 - 2/13(e)

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